3D-IC STCO Physical Design Engineer Intern
Posted on: March 19, 2023
Intel's Advanced Design (AD) team resides within the Design Enablement (DE) organization, which collaborates closely with our partners in process technology, IP, and products spanning client/server and networking products. The primary focus of AD is to guide process technology definition, and design prototypes in Intel's latest process technology, supporting Intel's internal and external design customers.
The future of Moore's Law: 3D-IC STCO
The Design Technology Pathfinding (DTP) organization in Design Enabling (DE) is chartered to identify and drive key strategic initiatives in the pathfinding of future technologies, as a holistic Design co-optimization across the Product stack from System architecture to silicon as we extend DTCO to STCO (System Technology Co-Optimization). The job requires partnering and leveraging domain experts across Intel and the EDA Eco-System
Run Place and Route to design convergence to establish STCO 2D-3D Physical design baseline, assess quality, perform design analysis and 3D PPA optimization
3D EDA evaluation and methodology development
Inter chiplet analysis and validation with Synopsys 3D-IC Compiler and Cadence3D Integrity
Identify design optimization opportunities (silicon, package, EDA, architecture configuration, methodology, etc.)
Analyze architecture critical paths to identify how to best take advantage of this technology
Identify machine learning opportunities for further optimization
Highly independent, creative, and out-of-the-box thinker
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Ph.D. degree in Electrical Engineering or Computer Engineering and 1+ year of relevant work experience - OR - a Master's degree in Electrical Engineering or Computer Engineering with 2+ years of relevant work experience in the following:
Physical Design, Place and Route Tools, Flows, and Methodology
Synopsys with Cadence Place and Route tools, design/sign off reference flows in advanced technologies
Deep understanding of design methodology and EDA tools for physical design
Scripting skills using a programming language such as Python, TCL
Digital and Circuit Design
Inside this Business Group
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.
Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
Annual Salary Range for jobs which could be performed in US, California: $63,000.00-$166,000.00
*Salary range dependent on a number of factors including location and experience
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
Keywords: Intel, Hartford , 3D-IC STCO Physical Design Engineer Intern, Engineering , Hartford, Connecticut
here to apply!